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TSMC Develops EMIB-Like Packaging Technology as Advanced Packaging Becomes Key Battleground

2026-08-01·newswire-us-stock-030621
TSMC Develops EMIB-Like Packaging Technology as Advanced Packaging Becomes Key Battleground.

TSMC is developing an advanced packaging technology similar to Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, as it faces competitive pressure from Intel in AI-chip packaging, according to reports.

People familiar with the matter said TSMC is working with Kinsus Technology, which is responsible for designing and manufacturing the substrate that carries the silicon bridges and connects components on top of the chips. TSMC currently uses Chip-on-Wafer-on-Substrate, or CoWoS, to package high-end AI chips.

CoWoS is the dominant advanced-packaging format, and AI chips from technology companies including Nvidia and AMD use the technology. TSMC’s existing CoWoS capacity is extremely tight. TSMC Chief Executive C.C.

Wei has publicly said that CoWoS capacity constraints are limiting customer growth, creating an opportunity for Intel to pursue customers that have traditionally relied on TSMC. EMIB, short for Embedded Multi-die Interconnect Bridge, is a cost-focused interconnect technology.

Unlike CoWoS, which places a single, expensive silicon interposer beneath the processor and memory, EMIB embeds small silicon bridges in the package substrate only where high-speed communication is needed. In theory, the design can reduce costs, improve chip-area utilization and support the integration of a larger number of chips.

As packaging becomes a capacity bottleneck in advanced semiconductor manufacturing, Intel is positioning EMIB as an alternative to TSMC’s CoWoS, according to the reports. Media reports from Wccftech, Tom’s Hardware and others said Intel’s EMIB technology has attracted interest from customers including Nvidia and Google.

Google plans to commission Intel to produce more than 3 million tensor processing units before 2028, while Nvidia is evaluating whether to use the technology in processors it plans to introduce.

Meanwhile, TSMC is expanding its packaging capabilities through several routes, including a plan to develop CoWoS glass substrates and the construction of a CoPoS pilot production line. As AI systems continue to push the boundaries of performance, scale and efficiency, advanced packaging is becoming a key driver of semiconductor innovation.

Leading companies across the industry are forming partnerships around packaging and developing competing technology paths. On July 25, Intel and Lens Technology announced a strategic partnership to jointly develop new advanced semiconductor packaging technologies, focusing on glass-substrate packaging solutions.

In May, BOE and Corning also signed a three-year memorandum of understanding covering glass-based packaging substrates, foldable glass, perovskite glass substrates and optical interconnects. Huawei recently released Taoding Law V2 and disclosed measured mass-production data for Kirin 2026.

BOCOM International Securities said the Kirin 2026 results show that logic folding currently has the capability for large-scale mass production in mobile devices, with advanced packaging serving as the process foundation for bringing logic folding into mass production.

The China-based research firm LeadLeo said China’s IC packaging-substrate market is expected to grow from USD 3.15 billion in 2025 to USD 5.63 billion in 2030, representing a compound annual growth rate of 12.3%.

It attributed the growth outlook to surging demand for AI computing power, rising adoption of advanced packaging and accelerating domestic substitution.

The firm said China’s IC packaging-substrate industry is expected to evolve in five areas: dielectric-material innovation, upgrades to integrated architectures, optimization of physical structures, expansion of application scenarios and faster domestic substitution.

These developments are expected to push products toward higher performance, greater integration and increased self-reliance. The source page was published on July 31, 2026.

#Stocks #Nvidia #Google #AMD #Intel

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TSMC Develops EMIB-Like Packaging Technology as Advanced Packaging Becomes Key Battleground

TSMC is developing an advanced packaging technology similar to Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, as it faces competitive pressure from Intel in AI-chip packaging, according to reports. People familiar with the matter said TSMC is working with Kinsus Technology, which is responsible for designing and manufacturing the substrate that carries the silicon bridges and connects components on top of the chips. TSMC currently uses Chip-on-Wafer-on-Substrate, or CoWoS, to package high-end AI chips. CoWoS is the dominant advanced-packaging format, and AI chips from technology companies including Nvidia and AMD use the technology. TSMC’s existing CoWoS capacity is extremely tight. TSMC Chief Executive C.C. Wei has publicly said that CoWoS capacity constraints are limiting customer growth, creating an opportunity for Intel to pursue customers that have traditionally relied on TSMC. EMIB, short for Embedded Multi-die Interconnect Bridge, is a cost-focused interconnect technology. Unlike CoWoS, which places a single, expensive silicon interposer beneath the processor and memory, EMIB embeds small silicon bridges in the package substrate only where high-speed communication is needed. In theory, the design can reduce costs, improve chip-area utilization and support the integration of a larger number of chips. As packaging becomes a capacity bottleneck in advanced semiconductor manufacturing, Intel is positioning EMIB as an alternative to TSMC’s CoWoS, according to the reports. Media reports from Wccftech, Tom’s Hardware and others said Intel’s EMIB technology has attracted interest from customers including Nvidia and Google. Google plans to commission Intel to produce more than 3 million tensor processing units before 2028, while Nvidia is evaluating whether to use the technology in processors it plans to introduce. Meanwhile, TSMC is expanding its packaging capabilities through several routes, including a plan to develop CoWoS glass substrates and the construction of a CoPoS pilot production line. As AI systems continue to push the boundaries of performance, scale and efficiency, advanced packaging is becoming a key driver of semiconductor innovation. Leading companies across the industry are forming partnerships around packaging and developing competing technology paths. On July 25, Intel and Lens Technology announced a strategic partnership to jointly develop new advanced semiconductor packaging technologies, focusing on glass-substrate packaging solutions. In May, BOE and Corning also signed a three-year memorandum of understanding covering glass-based packaging substrates, foldable glass, perovskite glass substrates and optical interconnects. Huawei recently released Taoding Law V2 and disclosed measured mass-production data for Kirin 2026. BOCOM International Securities said the Kirin 2026 results show that logic folding currently has the capability for large-scale mass production in mobile devices, with advanced packaging serving as the process foundation for bringing logic folding into mass production. The China-based research firm LeadLeo said China’s IC packaging-substrate market is expected to grow from USD 3.15 billion in 2025 to USD 5.63 billion in 2030, representing a compound annual growth rate of 12.3%. It attributed the growth outlook to surging demand for AI computing power, rising adoption of advanced packaging and accelerating domestic substitution. The firm said China’s IC packaging-substrate industry is expected to evolve in five areas: dielectric-material innovation, upgrades to integrated architectures, optimization of physical structures, expansion of application scenarios and faster domestic substitution. These developments are expected to push products toward higher performance, greater integration and increased self-reliance. The source page was published on July 31, 2026.

TSMC is developing an advanced packaging technology similar to Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, as it faces competitive pressure from Intel in AI-chip packaging, according to reports. People familiar with the matter said TSMC is working with Kinsus Technology, which is responsible for designing and manufacturing the substrate that carries the silicon bridges and connects components on top of the chips.

TSMC currently uses Chip-on-Wafer-on-Substrate, or CoWoS, to package high-end AI chips. CoWoS is the dominant advanced-packaging format, and AI chips from technology companies including Nvidia and AMD use the technology.

TSMC’s existing CoWoS capacity is extremely tight. TSMC Chief Executive C.C. Wei has publicly said that CoWoS capacity constraints are limiting customer growth, creating an opportunity for Intel to pursue customers that have traditionally relied on TSMC.

EMIB, short for Embedded Multi-die Interconnect Bridge, is a cost-focused interconnect technology. Unlike CoWoS, which places a single, expensive silicon interposer beneath the processor and memory, EMIB embeds small silicon bridges in the package substrate only where high-speed communication is needed. In theory, the design can reduce costs, improve chip-area utilization and support the integration of a larger number of chips.

As packaging becomes a capacity bottleneck in advanced semiconductor manufacturing, Intel is positioning EMIB as an alternative to TSMC’s CoWoS, according to the reports.

Media reports from Wccftech, Tom’s Hardware and others said Intel’s EMIB technology has attracted interest from customers including Nvidia and Google. Google plans to commission Intel to produce more than 3 million tensor processing units before 2028, while Nvidia is evaluating whether to use the technology in processors it plans to introduce.

Meanwhile, TSMC is expanding its packaging capabilities through several routes, including a plan to develop CoWoS glass substrates and the construction of a CoPoS pilot production line.

As AI systems continue to push the boundaries of performance, scale and efficiency, advanced packaging is becoming a key driver of semiconductor innovation. Leading companies across the industry are forming partnerships around packaging and developing competing technology paths.

On July 25, Intel and Lens Technology announced a strategic partnership to jointly develop new advanced semiconductor packaging technologies, focusing on glass-substrate packaging solutions. In May, BOE and Corning also signed a three-year memorandum of understanding covering glass-based packaging substrates, foldable glass, perovskite glass substrates and optical interconnects.

Huawei recently released Taoding Law V2 and disclosed measured mass-production data for Kirin 2026. BOCOM International Securities said the Kirin 2026 results show that logic folding currently has the capability for large-scale mass production in mobile devices, with advanced packaging serving as the process foundation for bringing logic folding into mass production.

The China-based research firm LeadLeo said China’s IC packaging-substrate market is expected to grow from USD 3.15 billion in 2025 to USD 5.63 billion in 2030, representing a compound annual growth rate of 12.3%. It attributed the growth outlook to surging demand for AI computing power, rising adoption of advanced packaging and accelerating domestic substitution. The firm said China’s IC packaging-substrate industry is expected to evolve in five areas: dielectric-material innovation, upgrades to integrated architectures, optimization of physical structures, expansion of application scenarios and faster domestic substitution. These developments are expected to push products toward higher performance, greater integration and increased self-reliance.

The source page was published on July 31, 2026.

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